In order to increase the performance and integration level of integrated circuit chips, the feature size of devices are continuously reducing according to the Moore's Law, and has now been reduced to a nanometer scale. With the reduction in the device volume, the power consumption and leak current has become the biggest concern, and a series of effects that could be ignored in the MOSFET long channel model become more and more notable and even become dominant factors affecting the performance. Such phenomena are collectively called the short channel effect. The short channel effect may cause the degradation of the electrical properties of the device, for example, a drop in the gate threshold voltage, an increase in power consumption and a reduction in signal-to-noise ratio, etc.
Such short-channel effects include, but art not limited to, drain-induced barrier lowering (DIBL) and saturation threshold voltage (Vtsat) roll-off. Specifically, DIBL refers to the fact that in a FET with a relatively short channel length the potential barrier that exists between the drain region and the source region is reduced by the electrostatic influence of the drain voltage. Vtsat roll-off refers to the fact that the relationship between channel length and the Vtsat is curved with significant Vtsat roll-off at smaller channel lengths. DIBL and Vtsat roll-off can both result in an increased off-state leakage current between the source and drain regions. Thus, there is a need in the art for a FET structure that allows for device scaling with minimal DIBL and Vtsat roll-off.